1. Field of Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method for preventing the diffusion of dopants in a dual gate device.
2. Description of Related Art
Mixed mode devices such as the one that incorporates logic devices into DRAM circuits are becoming more common. To obtain even lower operating voltages, CMOS having dual gates are often formed. Self-aligned silicide processes are frequently employed in the fabrication of dual gates. The silicide layer thus formed the capacity to lower the resistance between the gate terminal and the diffusion layer as well as to connect the N.sup.+ -type polysilicon gate terminal with the P.sup.+ -type polysilicon gate terminal. However, it is difficult for a DRAM connected via a silicide layer to maintain good refresh properties. Consequently, the dual gates of an embedded DRAM must be manufactured with polycide. However, the N.sup.- dopants or P.sup.- dopants in polycide gates can easily diffuse into each other leading to a shift in the threshold voltage. Therefore, a barrier layer is normally formed between the polysilicon layer and the polycide layer to limit the quantity of dopant cross-diffusion.
FIGS. 1A through 1C are schematic, cross-sectional views showing the progression of manufacturing steps according to a conventional method of fabricating a dual gate device.
First, as shown in FIG. 1A, a substrate 10 having two neighboring wells 14 and isolating structures 12 thereon is provided. Thereafter, thermal oxidation is used to form a gate oxide layer 16 over the substrate 10. Then, chemical vapor deposition (CVD) is used to form a polysilicon layer 18 over the gate oxide layer 16.
Next, as shown in FIG. 1B. a barrier layer 20 is formed over the polysilicon layer 18. The barrier layer 20 can be formed by first depositing a silicon-rich tungsten silicide layer (WSi.sub.x) over the polysilicon layer 18 using chemical vapor deposition (CVD). Then, tungsten nitride (WN.sub.x) or titanium nitride (TiN.sub.y) is deposited over the tungsten silicide layer by sputtering. The tungsten silicide layer together with the tungsten nitride or the tungsten silicide layer together with the titanium nitride layer forms the barrier layer 20.
Next, as shown in FIG. 1C, a conductive layer 22 is formed over the barrier layer 20. The conductive layer 22 can be a tungsten-rich silicide layer formed by chemical vapor deposition (CVD). Alternatively, the conductive layer 22 can be a tungsten layer formed by sputtering or chemical vapor deposition (CVD).
In the subsequent step, the P-type gate and the N-type gate are patterned, and then the source/drain regions are formed in the substrate to complete the fabrication of a dual gate transistor.
Although tungsten nitride and titanium nitride are capable of preventing the diffusion of boron ions, both tungsten nitride and titanium nitride are formed by a sputtering method. On the other hand, the polysilicon layer and the tungsten silicide layer are formed by chemical vapor deposition (CVD). Hence, reacting stations have to be switched twice during the fabrication of a dual gate transistor, thereby increasing cycle time and lowering the yield.
In light of the foregoing, there is a need to provide a method for fabricating a dual gate transistor capable of preventing the diffusion of dopants and having a shorter cycle time.